A Survey of Low Power High Speed Vedic Techniques in Current VLSI Design

Abstract

Developments in Machine Learning (ML) and Artificial Intelligence (AI) have impacted the integration of complicated designs in Very Large-Scale Integration (VLSI) Design. To meet the demands of technology, designers are focusing on low power and high speed methods. Digital signal processors are the building blocks of many AI applications; by optimising them, Vedic mathematics may be used to address problems with data signal processing at a quicker pace while using less power. The current applications of Vedic mathematics in the field of VLSI are thoroughly reviewed in this study in order to provide innovative designs and effective architectures for Squarer, Multiplier, Arithmetic unit, Cubic, and Divider circuits along with their essential performance requirements. It follows that the use of Vedic Sutras in