Distinct ρ-based model of silicon N-channel double gate MOSFET

Abstract

Metal-oxide-semiconductor (MOS) technology is used in the fields of very large scale integrated (VLSI) circuit technology to meet the ever-increasing need for digital processing technology. This technology allows for high-speed calculations with little propagation delay and low power consumption. However, in the current microelectronic regime, MOS technology is having trouble linearly scaling transistors with various channel modeling. Short-channel effects (SCEs) limit the MOSFET's linear scalability. With its variable input capacitance value ratio and appropriate forward transfer admittance, silicon N-channel double gate MOSFETs (DG MOSFETs) are used in the modern microelectronic regime to achieve the short channel effect of MOSFETs. In order to estimate the varying junction capacitances that can limit the use of intrusion detection systems (IDS) in VLSI applications, a unique ρ-based model is developed in this research paper to simulate SCEs using silicon N-channel double gate MOSFETs with varying front and back gate doping levels and surface regions. A simulated model for the total internal device capacitance using a different ρ-based model and an analytical model for the channel length are shown. Comparative findings demonstrate the efficacy of the suggested unique ρ-based model, which is appropriate for silicon nanowire transistors.